1. Field of the Invention
The present invention relates to an image signal coding apparatus and particularly, to a coding apparatus for encoding and outputting a moving image data in real time according to MPEG (Moving Picture Experts Group) standards.
2. Description of the Background Art
In general, compression processing according to MPEG 1 and MPEG 2 standards has been employed in order to encode a moving image data including a great amount of information efficiently. In the MPEG standards, processing is performed as follows: A picture of a field or a frame is divided into compression units called macroblocks. A macroblock of a reference picture having the highest correlationship with a macroblock of interest of a current picture is detected, difference values between corresponding pixels of the macroblocks having the highest correlationship are obtained and the difference values are encoded. In the MPEG standards, redundancy of moving image information and characteristics of a human visual organ are exploited, and redundant information and information unimportant in terms of a human visual characteristics are removed to compress moving image information. An amount of codes of digital information (a bit stream) obtained as a result of the compression varies to a great extent depending on characteristics of an input image, such as correlation degree between pictures (frames or fields) and an amount of high spatial frequency components, even under the same compression conditions. Therefore, an amount of codes resulting from the compression fluctuates even in one picture period. A target of an amount of codes is generally set for each picture (image), a compression parameter is controlled such that an amount of codes coincides with the target amount.
Coded image information have to be transmitted to a decoder through a transmission line. A bit stream buffer is used for transmitting a bit stream through a transmission line with a constant data transfer rate. In a period in which an amount of codes is great, a transmission amount is lowered by storing codes in excess of a transmission capacity in a bit stream buffer, while in a period in which an amount of codes is small, codes are read out from the bit stream buffer and transferred at a predetermined data transfer rate. Transmission of coded data at a constant transfer rate can be realized by smoothing of a data transfer rate through exploitation of a bit stream buffer.
FIG. 14 shows a configuration of an output section of a conventional moving image signal processing apparatus schematically. In FIG. 14, the moving image signal processing apparatus includes: a quantization circuit 901 receiving DCT (Discrete Cosine Transformation) coefficient data of a picture of a field or a frame in macroblock units and performing quantization thereof; a scanning sequence conversion circuit 902 converting a scanning order of DCT coefficient data quantized by the quantization circuit 901 according to a zigzag scanning method, for example; a variable-length coding circuit 903 performing variable-length coding of quantized data having the scanning order converted by the scanning sequence conversion circuit 902; a bit stream buffer 904 for storing variable-length codes from the variable-length coding circuit 903; and an output control circuit 905 reading out sequentially data stored in the bit stream buffer 904 and outputting the data at a constant data transfer rate. In the variable-length coding circuit 903, quantized DCT coefficient data from the scanning sequence conversion circuit 902 are subjected to variable-length coding, thus effecting compression of an information volume.
This image signal coding apparatus further includes: a code amount sum circuit 906 summing up an amount of codes, in macroblock units, generated by the variable-length coding circuit 903; and a rate control circuit 907 controlling an amount of generated codes by adjusting a quantizing scale of the quantization circuit 901 according to the sum from the code amount sum circuit 906. The rate control circuit 907 generally sets a target amount of codes to be generated in a following picture according to the sum of the code amount sum circuit 906 and adjusts a quantizing scale of the quantization circuit 901 such that an amount of codes generated actually in the following picture coincides with the target. The rate control circuit 907 adjusts an amount of generated codes in macroblock units such that an average of an amount of codes outputted from the variable-length coding circuit 903 coincides with a transmission rate on a transmission line through which a bit stream outputted from the output control circuit 905 is transmitted. This coding of one picture of a frame in macroblock units is carried out sequentially in one picture period of input images.
In coding of a picture (an image of a field or a frame), when an amount of codes does not reach a target, a byte data of xe2x80x9c0xe2x80x9d called as a stuff byte is generated and the stuff byte is added to a coded data such that an amount of generated codes of a picture coincides with a target. The term xe2x80x9cstuffingxe2x80x9d indicates an operation of inserting a stuff byte into a bit stream. The stuff bytes are discarded in decoding. A shortage of an amount of codes from a target can be filled up with stuff bytes with no adverse influence on a reproduced image.
This stuffing, in the MPEG 2 standard, can be performed in GOP (group of pictures) units, picture units or slice units and, in the MPEG 1 standard, can be performed in GOP units, picture units, slice units or macroblock units. Generally, stuffing is performed in picture units or sequence units in most cases. When stuffing is performed in macroblock units, a picture quality is degraded due to limitation of an amount of codes in each macroblock. For example, if stuffing is performed in picture units, an amount of codes can be allotted to individual macroblocks according to complexity thereof.
In a case of stuffing in picture units, the stuffing is performed after coding of one picture is completed and the sum of codes of the one picture is calculated.
FIGS. 15A and 15B are illustrations showing distributions in amount of stuff bytes and generated codes of macroblocks when an amount of coded data of one picture is close to a target schematically. As shown in FIG. 15A, stuff bytes are inserted after a region for placing coded data of one picture. When an amount of coded data of one picture is close to a target, amounts of codes in respective macroblocks, as shown in FIG. 15B, are large, but an amount of stuff bytes is small. When stuff bytes are inserted after a coded data store region for one picture, an amount of codes is summed in the code amount sum circuit 906 shown in FIG. 14 and stuff bytes are generated according to a result of the summing and stuff bytes generated are multiplexed with coded data to be written into the bit stream buffer 904. In this case, since a generation amount of stuff bytes is small, necessary stuff bytes can be generated and written in the bit stream buffer 904 with a sufficient margin.
FIGS. 16A and 16B are illustrations showing distributions of codes and stuff bytes when an amount of coded data of one picture is extremely small schematically. In FIG. 16, coded data of one picture are extremely small in amount. This phenomenon arises when a motion of a picture is extremely low in speed or amount in a prediction coding scheme. Since amounts of generated codes of macroblocks are small as shown in FIG. 16B, stuff byte tens of times as large as an amount of coded data of one picture are required to be generated.
Generation of the stuff bytes and a write operation thereof into the bit stream buffer 904 are executed in a period between pictures, for example in a vertical blanking period. In a case where a transmission rate of a bit stream is as high as several tens Mbps (bit/sec), an extremely large amount of stuff bytes are necessary to be inserted in order to transfer coded data in matching with the transmission rate. The bit stream buffer 904, however, is generally constructed of RAMs (Random Access Memories) and there is a limitation on a data transfer rate. Therefore, even in order to be adapted with a transfer rate of several tens Mbps, a data transfer capability of the bit stream buffer 904 is necessary to be sufficiently high so as to write a great amount of stuff bytes in the bit stream buffer 904, making the bit stream buffer 904 expensive. In another case, the bit stream buffer 904 cannot cope with this high data transfer capability requirement and a necessary amount of stuff bytes cannot be adequately inserted. Thus, it becomes impossible to smooth a data transfer rate, resulting in a problem such as processing failure in a decoder.
That is, since coding of picture data in one screen is sequentially carried out in one picture processing time, write operations of coded data on the bit stream buffer 904 are sequentially performed (the write operations are carried out in macroblock units). Since transfer of stuff bytes generated when coding of this one screen (one picture) is completed is executed after the completion of coding of the one picture, the stuff bytes are necessary to be generated and written at a higher rate than writing of coded data is. Therefore, a memory having a higher data transfer rate than necessary for smoothing a transfer rate of coded data is required to be used for the bit stream buffer 904 simply for the purpose of insertion of the stuff bytes, which entails use of a memory with a transfer rate higher than necessary, resulting in a problem of a cost of the coding apparatus being high.
It is an object of the present invention is to provide an image signal coding apparatus that can reduce a data transfer capability of a bit stream buffer memory.
It is another object of the present invention is to provide an image signal coding apparatus that can realize stuffing even with a memory having data transfer capability of the same level as an bit stream transfer rate.
It is still another object of the present invention is to provide an image signal coding apparatus that has no necessity of generating a great amount of stuff bytes in a short period.
It is yet another object of the present invention is to provide an image signal coding apparatus that can performs smoothing of data transfer in a correct manner with no overflow or underflow phenomenon even using a memory with a low data transfer capability as a bit stream buffer.
An image signal coding apparatus according to the present invention includes: bit stream generation circuitry for coding an image signal to generate a bit stream of coded image data; difference detection circuitry calculating the number of bits of coded image data for each predetermined processing unit section of a bit stream from the bit stream generation circuitry and obtaining a difference between the calculated number of bits and a predetermined reference number of bits; insertion circuitry generating a difference code indicating the difference detected by the difference detection circuitry and a stuff start code indicating an insertion position of the difference code, and outputting the bit stream to a bit stream memory after inserting the difference code and the stuff code into the processing portion of the bit stream; output circuitry extracting a stuff start code and a difference code from a bit stream read out from the bit stream memory and inserting stuff bits of the number indicated by the difference code into a corresponding processing unit section in accordance with the stuff start code and the difference code extracted, starting at a position indicated by the stuff start code, to output the bit stream with the inserted stuff bits; addition circuitry adding up an amount of data bits written in the bit stream memory and an amount of data bits indicated by the difference code; and subtraction circuitry subtracting an amount of stuff bits inserted by the output circuitry from an output value of the addition circuitry, to output a result of the subtraction when a difference code is extracted by the output circuitry.
The subtraction circuitry preferably further includes a circuit for subtracting an amount of data bits of a difference code and a stuff start code from an output value of the addition circuitry.
The stuff start code, in an aspect of the present invention, is a flag attached to a difference code and by this flag, a corresponding code can be identified as a difference code.
An image signal coding apparatus according to another aspect of the present invention includes: bit stream generation circuitry for coding an image signal to generate a bit stream of coded image data; difference detection circuitry calculating the number of bits of coded image data for each predetermined processing unit section of a bit stream from the bit stream generation circuitry and obtaining a difference between the calculated number of bits and a predetermined reference number of bits; insertion circuitry generating a difference code indicating a difference detected by the difference detection circuitry, outputting the coded image data with a flag of a first logic state linked thereto, to a bit memory, in a unit of a predetermined number of bits in parallel and outputting the difference code with a flag of a second logic state different from the first logic state linked thereto to the bit memory, in the unit of the predetermined number of bits in parallel; and output circuitry extracting a difference code according to a flag from a bit stream read out from the bit stream memory and inserting stuff bits by the number indicated by the difference code in a corresponding processing unit section in accordance with the difference code extracted, starting at a position indicated by a flag to output the bit stream with the inserted stuff bits.
An image signal coding apparatus according to a still another aspect of the present invention includes: bit stream generation circuitry for coding an image signal to generate a bit stream of coded image data; difference detection circuitry calculating the number of bits of coded image data for each predetermined processing unit section of a bit stream from the bit stream generation circuitry and obtaining a difference between the calculated number of bits and a predetermined reference number of bits; insertion circuitry generating a difference code indicating a difference detected by the difference detection circuitry and a stuff insert position indicating code indicating an inserting position of the difference code and generating a multiplexed bit stream by inserting the difference code and the stuff insert position indicating code into a corresponding processing unit section; a bit stream memory for storing a bit stream generated by the insertion circuitry; output circuitry extracting a difference code from a bit stream read out from the bit stream memory and inserting stuff bits by the number indicated by the difference code in a corresponding processing unit section in accordance with the difference code extracted, starting at a position indicated by the stuff insert position indicating code, to output the bit stream with the inserted stuff bits.
In the bit stream memory, stuff bits (stuff bytes) are not stored, but a difference code indicating the number of stuff bytes (bits) is stored. Therefore, there is neither a need to generate a great amount of stuff bits in a short time nor a need of a high transfer rate bit stream memory. Further, there is no need to generate a great amount-of stuff bits in a short time and even when an amount of generated codes is different according to characteristics of a picture, a bit stream memory can cope with such the situation correctly. Further, when a bit stream is transferred to a decoder, stuff bits are actually inserted according to a difference code, whereby the bit stream can be surely transferred at a constant data transfer rate.
Further, with a difference code, stuff bits are virtually stored in the bit stream memory and, by detecting a stored data amount of the bit stream memory when stuff bits were really stored in the bit stream memory, an amount of generated codes can be adjusted in a similar manner to a case where stuff bits are actually stored in the bit stream buffer memory.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.